The present invention relates to semiconductor devices, and more particularly, to a method of forming a micro pattern of a semiconductor device, in which the number of process steps can be reduced during a micro pattern formation process.
As the degree of integration of devices increases, the size of the minimum line width to be implemented is reduced. In order to implement a reduced micro line width due to the high integration of the devices, various process steps are required. To form a hard mask pattern for forming a micro pattern, a mask formation process, a Double Exposure Etch Tech (DEET) method or a spacer formation process having several steps must be carried out. The process method increases not only the overall number of process steps, but also device mass-production costs.